1. Field of the Invention
Present invention relates to an alignment check pattern, more particularly to an alignment check pattern for a multi-level interconnection of more than three levels.
2. Description of the Prior Art
Typically, the complexity of a multi-level interconnection structure used is in proportion to the degree of complexity of the integrated circuits. In a multi-level interconnection structure, it is necessary to improve alignment accuracy for certain connection between upper and lower level wirings via through holes which are formed in a interlayer insulating film. Because the through holes are provided for the interlayer insulating film in accordance with the location of lower level wirings, and the upper level wirings are patterned in accordance with the location of the through holes, it is necessary to raise the alignment accuracy of the horizontal direction with reference to each of the wirings and the through holes.
Alignment check patterns are formed on the surface of a substrate on which the multi-level interconnection structure is formed to confirm whether the alignment is as expected. The alignment check pattern may be called a vernier caliper.
An alignment check pattern to inspect the alignment between certain level wirings and a through hole provided in an interlayer insulating film which is formed between the wirings comprises a regular scale patterns formed at the same time as the patterning of the lower wirings and made of same material, and vernier scale patterns formed at the same time as the forming of openings at a photoresist film which is formed on the interlayer insulating film to provide through holes in the interlayer insulating film. The regular scale patterns are made up of a plurality of rectangular shape patterns arranged at the regular intervals. The vernier scale patterns are made up of a plurality of openings each having a rectangular shape formed at the photoresist film and arranged at the regular intervals which is not the same as the intervals of the regular scale patterns.
Detection of a misalignment amount at an alignment exposure is performed by observing the misalignment amount between the regular scale patterns and the vernier scale patterns using an optical microscope or the like.
According to the detection result, after adjusting the location where the mask pattern for forming contact holes is formed, openings are provided in the interlayer insulating film using the mask pattern as an etching mask. After removing the mask pattern, the upper level wirings are formed on a surface of the interlayer insulating film to fill in the openings. In this way, connections between the upper level wirings and the lower level wirings can be performed for at least a two level interconnection structure.
Due to an increase in the scale of semiconductor integrated circuit devices, a one or two level interconnection may be insufficient and a highly integrated, multi-level interconnection of at least three levels may become necessary. In the case of forming peripheral marks such as the alignment check patterns, accompanying the increase in the number of levels in multi-level interconnection, a step difference between an inside part of the integrated circuit and the peripheral mark part (such as the alignment check pattern) occur as a result of the absence of a lower metallic wiring formed below the regular scale patterns of the previous processing step. As the result of the step difference, the alignment exposure may become out of focus. Therefore, a problem is presented in that it is difficult to accurately expose both the inside integrated circuit part of the photoresist and the peripheral mark part of it at the same time.